1. Field of the Invention
The present invention relates to electronic circuits and more particularly to a device for transferring data between two asynchronous subsystems comprising a buffer storage.
2. Description of the Related Art
Many electronic circuits comprise independent sub-assemblies that are clock-actuated by absolutely asynchronous clocks. It is the case when, for example, a high-speed processor processes data and then needs to communicate with a lower speed system. There may be no relation between the phases of both system clocks compared to each other. This can even be the case within a single semiconductor circuit where two absolutely independent different subsystems clock-actuated by absolutely asynchronous clocks are arranged.
Techniques are well known that allow communication between asynchronous systems.
FIG. 1 illustrates a traditional technique, based on a transmit flag that accompanies data transmission from a system 100 to a system 150.
To this end, in sub-assembly 100, data transfer is organized from an input 101 (next_data) to a register 102 via a multiplexer 103 that is controlled by a control signal 114 (tx_send). The transmit flag tx_flag is generated by means of an XOR gate 104 and a flip-flop 105 ensuring a change of state for each new transmitted data.
On the other side, in receive subcircuit 150, flag signal tx_flag is received on the input of a flip-flop 151, and is then transmitted to an input of a second flip-flop 152 and finally to a third flip-flop 153. The respective outputs of flip-flops 152 and 153 (rx_flag) are used by an XOR gate 154 in order to generate a control signal (rx_receive) ensuring the transfer of received data (tx_data) to a register 156 via a multiplexer 157.
The major disadvantage of this first known system lies in the fact that the receive clock must be sufficiently fast to ensure reception of the data transmitted by sub-assembly 100. Otherwise, it results in data loss. More particularly, there must be two rising edges of clock signals of the receiving subsystem 150 between two successive switches of signal tx_flag. Thus, receive speed must be much higher than transmit speed. In particular, sub-assembly 150 that receives data does not have any possibility of slowing down the information stream transmitted by sub-assembly 100. Generally, such a structure can operate only for low transmit speeds.
FIG. 2 more particularly illustrates chronograms representative of the operation of the system described in FIG. 1, and in particular transmit signals tx_clk, tx_send, tx_flag and tx_data and, receive signals rx_clk, rx_flag, rx_receive and rx_data.
In order to slow down transmission of transmit information when that proves to be necessary, the receive sub-assembly can be equipped with a handshake mechanism. Such a technique is illustrated in FIG. 3: Sub-assembly 200 comprises, like previously, a register 202 for receiving the data presented to a circuit 201 and transmitted via a multiplexer 203 under control of signal tx_send. This signal tx_send is used to control a multiplexer 204 whose output is connected to a flip-flop 205 generating transmit flag tx_flag. A flip-flop 206 is connected in cascade with a flip-flop 207, which flip-flop has an output connected to a first switching input of multiplexer 204 and to a first input of an XOR gate 208. A second input of multiplexer 204 receives the transmit flag output from flip-flop 205. Gate XOR 208 outputs a signal tx_dont_send that is used to stop transmission of data.
On the receive side, transmit flag tx_flag is transmitted via a cascade of flip-flops 251 and 252 (switching according to the clock of subsystem 250) to a flip-flop 253 and to a first input of an XOR gate 254. Flip-flop 253 generates a second flag rx_flag that is transmitted, on the one hand, to the input of flip-flop 206 in subsystem 200 and, on the other hand, to a second input of gate XOR 254 controlling a multiplexer 255. This multiplexer allows the transfer of data received from sub-assembly 200 to a register 256, which register outputs data rx_data on a circuit 257.
As can be seen in chronograms of FIG. 4, receive flag rx_flag can now be sent back to sub-assembly 200 for controlling transmit speed of sub-assembly 200 that will be able to transmit again only when the change of state is reflected within the loop comprised of elements 251, 252, 253, 206, 207, 204 and 205.
Such a system is certainly more advantageous than the first system that was previously described because data loss is no longer to be feared. On the other hand, it still does not make it possible to increase data transmission speed.